Nonvolatile storage devices are widely included in mobile apparatuses such as cell phones and digital cameras, and the use of the nonvolatile storage devices is rapidly increasing. In recent years, opportunities for handling audio data and image data have been increasing, a strong demand for the nonvolatile storage devices having a larger capacity and operating faster than ever has started to grow. Moreover, a demand for low power consumption has been further increasing in the field of the nonvolatile storage devices for mobile apparatus.
Current nonvolatile storage devices are mainly flash memories. The flash memories store data by controlling charges accumulated in floating gates. The flash memories have a structure of accumulating, using a high electrical field, the charges in the floating gates, and thus a problem has been pointed out that there is a limit to downsizing of the flash memories and it is difficult to perform flash memory microfabrication necessary for a further increase in capacity. Moreover, the flash memories need to always collectively erase predetermined blocks for rewriting. With such a characteristic, it takes a very long time to rewrite the flash memories, and there is a limit to random access to and an increase in the speed of the flash memories.
Examples of next-generation nonvolatile storage devices solving the above problems include nonvolatile storage devices using variable resistance elements which store data by change in electrical resistance. Examples of nonvolatile semiconductor devices (also referred to as “nonvolatile memories”) using currently proposed variable resistance elements include MRAMs (Magnetic RAMs), PCRAMs (Phase-Change RAMs), ReRAMs (Resistive RAMs), and so on (refer to PTL 1 to PTL 3, for instance).
PTL 1 discloses an example of a method for controlling a bipolar ReRAM element using an oxide having a perovskite structure. Here, the term “bipolar” refers to a resistance change of the ReRAM element to a high resistance state caused by a voltage pulse having one of polarities which is applied to the ReRAM element, and a resistance change of the ReRAM element to a low resistance state caused by a voltage pulse having the other of the polarities which is applied to the ReRAM element. The ReRAM element is an element which can reversibly change between at least a first resistance state (also referred to as “low resistance state”, “LR state”, or simply “LR”) and a second resistance state (also referred to as “high resistance state”, “HR state”, or simply “HR”) having a higher resistance value than the first resistance state, and refers to a nonvolatile memory which stores data depending on one of the resistance states.
The following describes the method for controlling a ReRAM element with reference to the drawings.
Each of FIGS. 20 to 22 is a diagram showing a method for controlling a memory cell 9 disclosed in PTL 1. The memory cell 9 includes a variable resistance element 1 and a selection transistor 2. The variable resistance element 1 has one of terminals electrically connected to one of main terminals (drain and source) of the selection transistor 2. The selection transistor 2 has the other of the main terminals (source and drain) electrically connected to a source line terminal 3 via a source line 6. The variable resistance element 1 has the other of the terminals electrically connected to a bit line terminal 5 via a bit line 8. The selection transistor 2 has a gate electrically connected to a word line terminal 4 via a word line 7. In any one of the cases of writing data (writing “1” (here, data “1” assigned to the HR state of the ReRAM element)), erasing data (writing “0” (here, data “0” assigned to the LR state of the ReRAM element)), and reading data, applying a high-level turn-on voltage to the word line terminal 4 of a selected memory cell conducts the selection transistor 2.
FIG. 20 is a diagram showing an application state of a voltage pulse at the time of performing a write operation in the memory cell 9 in PTL 1. The source line 6 is set to 0 V (grounded), a positive write pulse having a predetermined write voltage is applied to the bit line 8, and desired data is written into the variable resistance element 1. When multivalued data is written into the variable resistance element 1, the voltage of the write pulse is set to a level corresponding to the value of the data to be written. For example, when four-valued data is written into the variable resistance element 1, one of four voltages predetermined according to each of the values of the data to be written is selected, and the write operation is performed. Moreover, an appropriate write pulse width is selected according to the element. In other words, a resistance change of the memory cell 9 to a predetermined resistance state requires a voltage level or a pulse width corresponding to the resistance state.
FIG. 21 is a diagram showing an application state of a voltage pulse at the time of performing an erase operation in the memory cell 9 in PTL 1. The bit line 8 is set to 0 V (grounded), and a positive erase pulse having a predetermined erase voltage is applied to the source line 6. The application of the erase pulse causes an electrical resistance of the variable resistance element 1 to be a minimum value. PTL 1 discloses applying an erase pulse to a specific source line 6 in a state where bit lines 8 are set to 0 V erases collectively and simultaneously memory cells connected to the bit lines 8 and the source line 6.
FIG. 22 is a diagram showing an application state of a voltage pulse at the time of performing a read operation in the memory cell 9 in PTL 1. When data stored in the variable resistance element 1 is read, the source line 6 is set to 0 V (grounded), and a predetermined read voltage is applied to a selected bit line 8 via a read circuit. Upon the application of the read voltage, a comparison and determination circuit compares a level of the bit line 8 with a reference level for reading, and the stored data is read.
PTL 2 and PTL 3 suggest a verify operation for verifying whether or not an electrical condition in which writing is performed to increase the reliability of data to be written satisfies a desired threshold value in a general semiconductor memory or ReRAM/variable resistance memory which allows electrical erasing and writing. To put it differently, in the case of data writing, as shown in FIG. 23, after a program command (e.g. “write”) is inputted (S51), application of a program pulse to a selected memory cell is started by inputting and latching addresses and data (S52), and the data is written into the memory cell (S53). After the application of the program pulse is stopped, a program verify mode is activated by inputting a program verify command (S54), and data reading from the memory cell into which the data has been written is started (S55). The data obtained through the data reading is compared with an expectation value data that is initially inputted (S56). When they match each other (YES in S56), the program is successfully ended, and a read mode is activated (S57). In contrast, when they do not match each other (NO in S56), the program pulse is applied again, and additional writing is performed (S51 to S53). This series of operations is repeated until all of data match each other. For practical purposes, however, an upper limit of repetition is often set to avoid an infinite loop. FIG. 24 is a timing diagram showing that a program is ended because expectation value data matches written data the third time a series of operations for a verify operation is performed after a program pulse is applied. Such a verify operation allows a physical characteristic written into a nonvolatile memory to reach a desired level, allows a margin for a threshold value used for determination to restore data to original digital data, and ensures a further increase in data reliability.